II. Model Interpretation

PXI: 3U PXI standard bus, single slot, compatible with PXI/PXIe chassis.

5404: NI 5400 series waveform generator, meaning:

54xx: Arbitrary waveform / function generator series

x4x: Analog output, bandwidth 100 MHz level

xx04: 1 channel, 12-bit, 105 MHz high-frequency version (compared to 5402: 20 MHz, 14 bits)

Component number: 778577-02 (standard configuration for PXI-5404).

III. Technical Parameters (25℃, 50 Ω terminal, typical values)

1. Basic Performance

Channel number: 1 sine (SINE) + 1 clock (CLOCK) synchronous output

Resolution: 12-bit DAC

Bandwidth (–3 dB): 105 MHz (sine / clock)

Sine output amplitude: 1–2 Vpp (±0.5–±1 V) @ 50 Ω; <9 kHz amplitude roll-off NI

Clock output amplitude: 5 V/3.3 V/1.8 V (TTL/CMOS) @ high resistance NI

Output impedance: sine 50 Ω; clock high resistance

Sampling rate: 300 MS/s (DDS direct digital synthesis)

Frequency resolution: 1.07 Hz (DDS, phase continuous)

2. Frequency Range

Sine (SINE): 9 kHz–105 MHz (effective)

Clock (CLOCK): DC–100 MHz (square wave, duty cycle 50%)

Frequency stability: ±0.2 dB (9 kHz–100 MHz)

3. Storage and Synchronization

Waveform memory: 8 MB (standard waveform storage)

Synchronization technology: PLL lock-in loop (external reference 10 MHz), NI-TClk multi-card synchronization NI

Trigger / Clock: PXI trigger bus, REF IN/OUT (10 MHz reference)

4. Environment and Power Consumption

Operating temperature: 0–50℃

Storage temperature: –40–70℃

Power consumption: approximately 15 W

Size: 3U single slot (about 160×100 mm)

IV. Interface and Communication Configuration

Front panel (single slot cover)

SINE (BNC): sine output, 50 Ω, ±1 Vmax

CLOCK (BNC): clock output, high resistance, 5 V/3.3 V/1.8 V selectable

REF IN (BNC): external reference clock input (10 MHz, PLL lock-in)

REF OUT (BNC): internal 10 MHz reference output

PFI0 (SMB): programmable trigger input / output

Bus and system interface

PXI backplane: 32-bit PCI, PXI trigger bus (TRIG0–TRIG6), RTSI

Synchronization clock: can route internal sampling clock / reference clock to:

front panel REF IN/OUT, PFI0

PXI trigger bus, RTSI bus (multi-card synchronization)

Software driver

Driver: NI-FGEN (standard configuration)

Support environment: LabVIEW, TestStand, Python, C#, LabWindows/CVI

Configuration tool: NI MAX (device management / calibration), soft front panel SFP

V. Core Functions

High-frequency dual-output synchronous: 105 MHz sine + 100 MHz clock synchronous output, meeting digital / analog mixed testing requirements NI. DDS Precise Frequency Synthesis: 1.07 Hz resolution, continuous phase frequency hopping / sweeping, low jitter square wave output.

Multilevel Clock Drive: 5 V/3.3 V/1.8 V compatible TTL/CMOS logic, directly drives digital circuits NI.

PLL External Reference Locking: Synchronous to 10 MHz external reference, ppb level frequency accuracy, multi-instrument phase coherence NI.

Standard Waveform Generation: Built-in sine, square, triangle, sawtooth, noise, DC; no arbitrary waveform function (different from 5402).

Six. Application Scenarios

ATE Automatic Testing: Digital chip clock synchronization, analog circuit high-frequency excitation, mixed signal function verification.

Semiconductor Testing: High-speed logic chips, RF chips, ADC/DAC clock and excitation testing.

Digital System Design: FPGA/CPLD clock source, high-speed interface (USB/PCIe) timing verification.

Automotive Electronics: High-frequency sensor simulation, vehicle communication module (CAN/LIN) clock synchronization.

Research and Education: High-frequency physics experiments, RF signal simulation, digital timing teaching experiments.

Seven. Usage and Maintenance Instructions

1. Installation and Power On

Power off installation, single slot fixed; chassis reliable grounding to prevent static electricity.

Power on preheating for 15 minutes, NI MAX self-check without hardware errors.

Keep ventilation during operation, temperature ≤ 50℃, do not block the chassis fan.

2. Wiring and Operation

High-frequency signals use 50 Ω high-precision coaxial cable, BNC tightened, to reduce reflection.

Sine output prohibits short circuit; load must be 50 Ω to avoid overcurrent damage.

Clock output connected to high-resistance load to avoid level pull-down; high frequency (>10 MHz) prefer AC coupling.

Multi-card synchronization: Enable PLL locking, share 10 MHz reference clock to ensure phase consistency.

3. Calibration and Maintenance

Calibration cycle: Suggested 2-year 1-time NIST traceable calibration; daily use internal self-calibration to compensate for temperature drift.

Interface maintenance: Regularly clean BNC/SMB interfaces to keep dry; long-term idle add dust cap.

Environmental Requirements: No condensation, humidity 10%–90% RH; away from strong electromagnetic interference and vibration.

Prohibited: Power-on unplugging cables, severe vibration, overheating operation.