II. Model Interpretation

PXI: 3U single-slot PXI module, compatible with PXI/PXIe mixed slots.

6562: 656x (LVDS differential high-speed waveform instrument); 2 = 200 MHz (6561 = 100 MHz).

Core Identifier: 16-channel LVDS differential, 200 MHz, DDR 400 Mb/s, SMC synchronous core, deep memory, ultra-low jitter.

III. Technical Parameters (25℃) General

Channel: 16 LVDS differential bidirectional I/O (each channel has independent direction in SDR mode).

Level: Standard LVDS (±350 mV differential), compatible with high-speed differential interface.

Drive: Differential drive, strong anti-common-mode interference, low power consumption.

Memory: 2/16/128 Mbit per channel (depending on model), ultra-long waveform storage.

Rate and Timing

Clock: Maximum 200 MHz (internal / external / reference), range 48 Hz to 200 MHz.

Data Rate: SDR = 200 Mb/s, DDR = 400 Mb/s (dual-edge sampling).

Edges: Rising / Falling / Delayed edges are programmable, channel skew ±400 ps (typical).

Trigger: PXI trigger bus, STAR trigger, 4-channel PFI, minimum pulse width 30 ns.

Synchronization: SMC (Synchronous with Storage Core), multi-module nanosecond-level synchronization.

Jitter: Typical 12 ps rms (cycle), meets ultra-high-speed differential timing requirements.

Physics and Environment

Size: 3U single slot (160×100 mm).

Power Consumption: Typical 16.4 W, maximum 20 W.

Connectors: 12-channel InfiniBand (LVDS I/O) + 3×SMB (clock / trigger).

Temperature: 0 to 55°C (commercial); extended grade -40°C to +85°C.

IV. Interface and Communication Configuration

Hardware Interface

I/O: InfiniBand connector, recommended dedicated LVDS shielded cable to ensure 200 MHz signal integrity.

Clock / Trigger: 3×SMB (CLK IN/OUT, PFI), supports external 200 MHz clock input.

Bus: PXI bus, DMA master mode, low CPU usage.

Software and Drivers

Driver: NI-HSDIO, paired with Digital Waveform Editor waveform editing software.

Development Environment: LabVIEW, Python, C#, TestStand, supports script sequences, PRBS generation, protocol simulation.

Synchronization: PXI trigger / RTSI/STAR, mixed-signal synchronization with digitizer, AWG.

V. Core Functions

16-channel LVDS differential ultra-high-speed bidirectional I/O: standard LVDS level, strong anti-interference, high rate, low power consumption; each channel has independent direction in SDR mode, flexible configuration of differential bus.

200 MHz clock + 400 Mb/s DDR: generate / capture ultra-high-speed differential timing, protocol signals (PCIe, HDMI, DisplayPort, Ethernet PHY, LVDS); ±400 ps skew, meets high-end timing verification requirements.

Ultra-large memory + advanced sequences: each channel up to 128 Mbit, storage of ultra-long differential waveforms; supports loop, branch, conditional triggering, PRBS, simulating complex differential communication.

SMC synchronous core: multi-module synchronization expanded to hundreds of channels, nanosecond-level alignment; seamless integration of digitizer, AWG, power supply, building high-end mixed-signal ATE.

Low noise and high stability: differential design suppresses common-mode noise, suitable for industrial strong interference, long-distance transmission; programmable input filtering, improving signal integrity.

VI. Application Scenarios

High-end LVDS/PCIe interface chip verification: timing / function testing, protocol simulation, signal integrity verification of PCIe, HDMI, DisplayPort, LVDS transceivers. High-speed communication equipment testing: 10G Ethernet PHY, differential signal testing of optical fiber communication modules, timing compliance, bit error rate testing.

High-end FPGA/SOC interface verification: FPGA/CPLD, LVDS high-speed buses of SoC, parallel interfaces, clock synchronization testing.

Automotive electronics and industrial control: On-board ADAS, autonomous driving, high-speed differential I/O of industrial PLC, long-distance communication, strong interference testing.

High-end mixed-signal ATE: PCB functional testing, simulation of ultra-high-speed differential interfaces, synchronous analog measurement (voltage/current).

VII. Installation and Maintenance Instructions

Installation and Power On

Installation: Power off, insert into the 3U slot of the PXI chassis, ensure reliable grounding of the chassis, and perform anti-static operation.

Power On: NI-HSDIO will automatically self-check after startup, no preheating required; avoid frequent cold-hot restarts.

Environment: Keep the air duct unobstructed, 0-55℃; avoid strong electromagnetic interference (motors, frequency converters).

Connection and Operation

Connection: Avoid frequent plugging and unplugging of InfiniBand interfaces, use dedicated LVDS shielded cables; ensure equal length and impedance matching of differential pairs to reduce skew and crosstalk.

Level Configuration: Confirm that the DUT is standard LVDS, prohibit mixing with single-ended TTL/CMOS to prevent damage.

High-speed Design: Strictly match impedance for 200 MHz signals, short traces, complete ground plane, to ensure signal integrity.

Daily Maintenance

Interfaces: Regularly clean InfiniBand/SMB interfaces, prevent dust and moisture; install dust covers when idle.

Software: Update NI-HSDIO drivers and firmware to obtain function optimization and bug fixes.

Calibration: Digital circuits do not require regular calibration; check wiring tightness and cable integrity annually.