PXI-2570
May 27, 2026

PXI-2570

I. Product Introduction The PXI-2570 (Part Number: 778572-70) is a 3U PXI high-density general-purpose SPDT latch relay module launched by National Instruments (NI). This module integrates 40 independent SPDT (Form C) latch relays in a single slot, balancing high density and high bandwidth signal switching. The module features low on-resistance, low thermal offset, 40 MHz bandwidth, latch-saving energy characteristics, supports 32,000 hardware scan lists and PXI backplane triggering, is compatible with PXI/PXIe mixed slots, and is suitable for precise analog signal switching, high-frequency testing, wiring harness inspection, multi-channel data acquisition, and low-power long-term值守 scenarios.

Description

II. Model Interpretation

PXI: Compliant with the PXI industrial bus standard, can be used in PXIe mixed slots.

2570: The model code of the NI universal relay module series, representing a 40-channel SPDT latch-type electromechanical relay.

Full name: PXI-2570 40-Channel SPDT PXI Relay Module.

Topology identifier: NISWITCH_TOPOLOGY_2570_40_SPDT, the hardware topology is fixed and cannot be reconfigured by software.

III. Technical Parameters

(1) Switching and Electrical Characteristics

Topology: 40 independent SPDT (Form C) latches, each channel includes COM (common terminal), NO (normally open terminal), and NC (normally closed terminal).

Relay type: Electromechanical latch relay, gold-plated contacts, pulse-driven coil (power consumption only during switching moment).

Maximum switching voltage: 100 VDC / 100 Vrms (CAT I), pulse withstand voltage 500 V.

Single-channel maximum switching/carrying current: 1 A.

Maximum switching power: DC 60 W, AC 62.5 VA (DC~60 Hz).

On-state resistance: Typical value < 50 mΩ.

Thermal offset: Typical value < 1 µV.

Operating bandwidth: DC ~ 40 MHz.

Action time: Typical 1.5 ms, maximum 3 ms.

Insulation withstand voltage: 150 Vrms between channels, between channel and ground.

(2) Life and Scan Parameters

Mechanical life: 2×10⁷ on-off cycles.

Full-load electrical life: 1×10⁵ on-off cycles.

Scan list: Maximum 32,000 programmable scan sequences.

Full-channel scan rate: Up to 145 times/second.

(3) Trigger and Control

Trigger channels: Support hardware trigger from PXI backplane Trigger 0 to Trigger 7 bus.

Minimum trigger pulse width: 150 ns (when digital filtering is disabled).

Onboard functions: Each relay channel has an independent counter for life monitoring; latch state is maintained when power is off.

(4) Physical and Environmental Parameters

Form specification: Standard 3U PXI single-slot module.

Front-end connector: 100-pin D-SUB female connector.

Form size: 216 mm × 20 mm × 130 mm.

Weight: Approximately 0.35 kg.

Power supply: PXI backplane 5 V power supply, typical power consumption 3.5 W (almost zero power consumption in latch state).

Operating temperature: 0 ℃ ~ 55 ℃.

Storage temperature: -20 ℃ ~ 70 ℃.

Relative humidity: 5% ~ 85%, no condensation.

IV. Interface and Communication Configuration

Front-end I/O Interface

All external signals are led out through 100-pin D-SUB female connector, including 40 complete SPDT channels (COM/NO/NC), and the remaining pins are shielding ground and reference ground. Electrical isolation between channels, a single-channel failure does not affect other channels; when the latch relay is de-energized, it maintains the current state, and no continuous power supply is required.

Bus and Software Communication

Bus interface: Standard PXI backplane bus, automatically acquires power, clock, and trigger signals, compatible with PXIe chassis mixed slots.

Driver: Standard NI-SWITCH driver, compliant with IVI specification.

Software support: Compatible with LabVIEW, TestStand, LabWindows/CVI, Python, etc. Basic functions: NI MAX can perform hardware identification, channel status reading, scan editing, trigger configuration, on-off count query, and latch state setting.

Synchronization capability: Relying on the PXI trigger bus, it realizes high-precision synchronous switching of multiple modules and instruments.

VII. Core functions

High-density SPDT switching: 40 SPDT channels in a single 3U slot, including common terminals / normally open / normally closed, suitable for complex signal routing.

Low-power latch design: Only consumes power during switching, zero power consumption in steady state, suitable for long-term monitoring and low-power testing systems.

High-frequency precise signal processing: 40 MHz bandwidth, low on-resistance, low thermal offset, suitable for high-frequency analog and low-level precise signals.

High-speed programmable scan: 32,000-step scan list, executed by hardware automatically, improving the throughput of automated testing.

Hardware synchronous trigger: PXI backplane trigger, precise timing, meeting requirements for high-speed parallel testing and multi-instrument collaboration.

Relay life monitoring: Board-mounted counter records the number of on-off cycles in real time, supporting predictive maintenance, reducing downtime.

Power-off state retention: Locks the relay's state after power-off and retains the channel status upon restart without the need for reconfiguration, enhancing system stability.

VI. Application scenarios

High-frequency automated testing of semiconductors / electronic components, precise signal selection and routing of multiple pins.

Automotive electronic testing, detection of high-frequency signals, low-voltage control circuits on/off and state retention.

Industrial data acquisition systems, multipoint sensor signals multiplexing and switching.

Industrial ATE equipment, precise control signal switching and long-term值守 for multiple paths of high-power load programming.

Laboratory research and development platform, high-frequency signal routing, circuit switching, comparison testing and low-power verification.

Large-scale distributed measurement and control system, high-density switch array, unified scheduling of multiple high-frequency / precise test signals.

Battery-powered, low-power long-term monitoring system, using latch characteristics to reduce energy consumption.

VIII. Usage and Maintenance Instructions

Usage points

Installation: Insert into a 3U standard slot, tighten the panel screws, keep away from strong vibration and strong electromagnetic interference; PXIe chassis should preferentially use mixed slots.

Connection: Use matching 100-pin D-SUB cables, gently insert and remove; use shielded cables for precise/high-frequency signals and reliably ground them to reduce interference.

Electrical limits: Strictly follow the 100 V/1 A rated parameters, prohibit overpressure and overcurrent; connect a shunt diode for inductive loads to prevent reverse high voltage from damaging contacts.

Trigger mode: Use software for debugging trigger; use PXI hardware for multi-module synchronization / high-speed scanning to ensure precise timing.

Power-on specification: Connect cables first, then power on; disconnect signal cables before unplugging; prohibit power-on while unplugging; automatically retain latch state after power-off, no need for repeated settings.

Maintenance instructions

Regular inspection: Inspect D-SUB connectors quarterly, clean dust, check for looseness and oxidation, ensure good contact.

Life management: Regularly read the number of on-off cycles using NI- SWITCH, plan to replace relays in advance when the load condition approaches 1×10⁵ times (support single-path replacement on-site).

Environmental control: Maintain dry and ventilated conditions, temperature 0~55 ℃, avoid condensation and dust accumulation, prevent contact oxidation.

Fault handling: First check wiring, grounding and trigger configuration for abnormal channels; single-path relay failure can be replaced on-site without replacing the entire module.

Storage requirements: Disconnect cables when not in use, install dust-proof protection on interfaces, store in a dry environment at -20~70 ℃, away from high temperatures, corrosion and strong magnetic fields.

Calibration: It is recommended to conduct a function check once a year, test the on-off status, on-resistance, bandwidth and latch retention performance to ensure testing accuracy.


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