2. Main CPU Models

CP451-10/51

• Processor: 32-bit RISC, 400 MHz

• Memory: 128 MB ECC RAM (battery-backed, 72-hour data retention)

• Application: Standard FCS for small-to-medium control loops.

CP461-50 S1

• Processor: High-performance 32-bit RISC

• Memory: 128 MB ECC RAM

• Application: Large-scale plants with complex control strategies; supports up to 3,000 function blocks.

CP471-00 S1

• Processor: Proprietary high-speed RISC

• Communication: Optimized for Vnet/IP and Ethernet data handling

• Compatibility: CS3000 R3 and later; 1:1 redundant support.

CP701/S1

• Processor: 64-bit RISC (VR5432 or equivalent)

• Memory: Up to 256 MB ECC RAM

• Application: High-end FCS, compatible with CS3000 and CENTUM VP systems; advanced control (e.g., multivariable control).

VC401-10

• Processor: 32-bit RISC

• Program Memory: 1 MB

• I/O Capacity: Up to 640 I/O tags per FCS

• Redundancy: Synchronous hot-standby, failover <100 ms.

3. Core Specifications

Processing & Performance

• Architecture: 32-bit/64-bit RISC; 64-bit floating-point arithmetic support.

• Control Cycle: Minimum 50 ms (deterministic scan).

• Execution Speed: ~0.1 ms per 1,000 instructions (typical).

• Function Blocks: Up to 3,000 (model-dependent).

Memory

• Type: ECC (Error-Correcting Code) RAM; battery-backed SRAM.

• Capacity: 16 MB–256 MB (model-dependent).

• Data Retention: 72 hours (battery backup, no power).

Communication Interfaces

• Vnet/IP: Redundant control network (1 Gbps); connects FCS to HIS/ENG.

• Ethernet: 10/100 Mbps; for engineering, HMI, and plant network integration.

• ESB/RIO Bus: Internal I/O bus; connects to local/remote I/O modules.

• Serial Ports: Optional RS-232/485 for third-party device communication.

Environmental & Electrical

• Operating Temperature: 0°C to +50°C (standard); -20°C to +60°C (extended, VC401-10).

• Humidity: 20%–80% RH (non-condensing).

• Power Supply: 24 VDC (backplane-fed, redundant power units).

• Certifications: IEC 61508 SIL 2, CE, UL, CSA.

4. 4-CPU Redundancy (Pair & Spare)

• Architecture: Two CPU modules (left/right), each with 2 independent CPUs; 4 CPUs operate in synchronous lockstep.

• Operation:

  1. All I/O data is fed to both CPU pairs simultaneously.

  2. Each pair’s two CPUs execute identical logic and cross-compare results.

  3. If results match, the pair outputs control commands; if mismatched, the other pair validates data to eliminate transient errors.

  4. On failure of one pair, the standby pair takes over seamlessly (<100 ms) with zero output disruption.

• Benefits: Tolerates both hardware faults and electromagnetic interference; “zero-downtime” continuous control.

5. Key Functions

Real-Time Control

• Analog PID, sequential logic, batch control, and advanced algorithms (e.g., model predictive control).

• Deterministic 50 ms scan for critical loops.

Data Processing

• I/O signal acquisition (analog/digital); alarm/event logging; historical data buffering.

• Trend calculation and data exchange with HIS/ENG via Vnet/IP.

Redundancy & Synchronization

• Real-time data mirroring between redundant CPUs (20 ms update interval).

• Automatic failover with no loss of control or data.

Online Maintenance

• Online 组态 (configuration changes), parameter tuning, and hot-swap of CPU/I/O modules without process shutdown.

• LED status indicators (POWER, RUN, RDY, ERR, COM) for diagnostics.

6. Application