PXIe‑6547
Description
Model Explanation
PXIe: PXI Express bus, 3U size, Gen1 x4, single slot.
6547: 6500 series, 100 MHz (SDR)/200 MHz (DDR), 32 channels, single-ended, with hardware comparison, without PMUNI.
Key Identifiers: Bidirectional I/O, Hardware Comparison, 100 MHz, Multi-level, Large-capacity Memory, Multi-module Synchronization.
Technical Parameters (Core)
Channels and Electrical
32 single-ended bidirectional I/O, each channel has independent input/output configuration by NI.
Logic Level: Software selectable 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V; Output Resolution 100 mV, Input Resolution 50 mV.
Input Voltage Range: -1 V ~ +4 V; Output Drive: 24 mANI per channel.
Clock and Performance
Maximum Clock: 100 MHz (SDR), 200 MHz (DDR).
Data Rate: Maximum 200 Mbit/s by NI.
Onboard Memory: Standard version 1 Mbit/channel, high-end 64 Mbit/channel.
Clock System: 800 MHz VCO + 32-bit DDS, resolution 0.2 Hz, accuracy ±150 ppm.
Synchronization: Multi-module / multi-box synchronization, channel-to-channel jitter ≤1 ns.
Hardware Comparison (Feature)
Supports real-time hardware comparison for bit error rate (BER) testing, protocol verification, fault injection by NI.
Bit-by-bit comparison, mask, error counting, stop-on-error function.
Physical and Environment
Size: 3U (21.6 × 2.0 × 13.0 cm) by NI.
Weight: Approximately 519 g by NI.
Power Consumption: Typical 32 W by NI.
Operating Temperature: 0 °C ~ +55 °C by NI.
Interface and Communication Configuration
1) Host Bus Interface
PXIe Gen1 ×4, single slot, plug-and-play, supports DMA, throughput: input 660 MB/s, output 400 MB/s by NI.
Supports PXI trigger bus, RTSI real-time synchronization, facilitating timing alignment of multiple devices by NI.
2) Front Panel I/O Interface
68-pin VHDCI (DDC): 32 digital I/O, sampling clock output, STROBE, event / trigger signal.
3 SMA:
CLK IN: External sampling clock / reference clock input (5–100 MHz).
CLK OUT: Reference clock / sampling clock output.
PFI 0: Programmable trigger / event I/O.
3) Driver and Software Communication
Driver: NI-HSDIO (compatible with IVI) by NI.
Development Environment: LabVIEW, C/C++, Python, TestStand by NI.
Configuration Tool: NI-MAX (Hardware Identification, Self-Test, Calibration) by NI.
Core Functions
32-channel bidirectional high-speed waveform generation / acquisition, supports SDR/DDR dual mode.
Hardware real-time comparison and error testing, suitable for communication / storage / interface protocol verification by NI.
Multi-level (1.2–3.3 V) software programmable, covering mainstream low-voltage digital devices.
Large-capacity onboard memory (up to 64 Mbit/channel), supporting ultra-long test sequences.
Nanosecond-level timing control and synchronization, channel-to-channel jitter ≤1 ns.
Multi-module / multi-box synchronization, building large-scale parallel test systems. Applicable scenarios
High-speed digital interface testing: Verification and BER testing of protocols such as DDR, SPI, I²C, UART, LVCMOS, etc. by NI.
Semiconductor and memory testing: Function and timing verification of Flash, SRAM, logic devices by NI.
FPGA/MCU verification: Generation of stimuli, capture of responses, timing tolerance testing, fault injection by NI.
Display/Image sensor: Testing of high-speed digital interfaces (such as MIPI), signal integrity verification by NI.
Aerospace/defense: Timing synchronization, status monitoring, error rate assessment of high-reliability digital systems by NI.
User and maintenance instructions
Key points of use
Installation: Single slot in a standard 3U PXIe chassis, recommended high-reliability chassis such as PXIe-1085 by NI.
Cabling: Use SHC68-C68-D4 shielded cable, length ≤ 1 m for high-frequency applications; use 50 Ω coaxial for SMA clock lines.
Configuration: Set NI-MAX for levels, clocks, triggers; configure NI-HSDIO for waveforms, sequences, comparison masks by NI.
Timing: Strictly control cable length and grounding for high-frequency applications to reduce crosstalk; calibrate the reference clock before synchronization by NI.
Maintenance and calibration
Cleaning: Regularly wipe the panel and connectors with a dry soft cloth to prevent static electricity by NI.
Calibration: Digital I/O does not require frequent calibration; it is recommended to check levels, drive currents, and timing accuracy every 2 years by NI.
Storage: −20 °C ~ +60 °C, humidity ≤ 60%, packaged with anti-static protection by NI.
Troubleshooting: First check wiring, power supply, and software configuration; check cables/grounding for timing abnormalities; check if the output is abnormal by checking if the load is short-circuited by NI.
Get a Quote