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PXIE-5641R

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PXIE-5641R
May 27, 2026

PXIE-5641R

The PXIe-5641R is a reconfigurable 2-input/2-output IF transceiver from National Instruments, integrating a Xilinx Virtex-5 SX95T FPGANI. Designed for software-defined radio (SDR), real-time spectrum analysis, and RF prototyping, it covers 250 kHz to 80 MHz IF range with 20 MHz real-time bandwidth. It combines high-speed ADCs/DACs, digital downconverters (DDCs), and digital upconverters (DUCs) to deliver flexible, high-performance IF signal processing in a compact PXIe form factor.

Description

Model Nomenclature

  • PXIe: PXI Express high-speed modular instrumentation bus.

  • 56: NI PXI RF/IF test and measurement series.

  • 41: Dual-channel IF transceiver with 20 MHz bandwidth, FPGA-based reconfigurability.

  • R: Reconfigurable (user-programmable FPGA via LabVIEW FPGA).

Technical Specifications

  • Form Factor: 3U PXIe module, single-slot width.

  • IF Frequency Range: 250 kHz to 80 MHz.

  • Real-Time Bandwidth: 20 MHz.

  • Input Channels: 2 (SMB connectors, 50 Ω).

  • ADC: 14-bit, 30 MS/s to 100 MS/s sampling rate, 20 MHz DDC per channelNI.

  • Output Channels: 2 (SMB connectors, 50 Ω).

  • DAC: 14-bit, 30 MS/s to 200 MS/s sampling rate, 20 MHz DUC per channelNI.

  • FPGA: Xilinx Virtex-5 SX95T (94,208 logic cells, 640 DSP blocks).

  • Onboard Memory: 128 MB DRAM, up to 1,600 MB/s data rate.

  • Noise Floor: -143 dBm/Hz (typical).

  • Output Power: Up to +2 dBm (50 Ω)NI.

  • Reference Clock: External 10 MHz (SMA), internal oscillator optional.

  • Trigger: PXI trigger bus, external TRIG (SMA, 3.3 V TTL)NI.

  • Operating Temperature: 0 °C to 55 °C; Storage: -40 °C to 70 °C.

Interface and Communication Configuration

  • Bus: PXIe Gen1 x1, supports peer-to-peer streaming and high-speed DMANI.

  • Drivers: NI-5640R, IVI-COM; compatible with LabVIEW, C/C++, Python, .NETNI.

  • Software: NI-MAX (configuration), LabVIEW FPGA (custom FPGA programming), NI-SDR toolkitsNI.

  • Synchronization: PXI trigger bus, RTSI, NI-TClk for multi-module phase alignmentNI.

  • I/O Connectors: 2×IF In (SMB), 2×IF Out (SMB), 1×10 MHz Ref In (SMA), 1×TRIG In (SMA).

Core Features

  • Dual IF Input/Output: Simultaneous acquisition and generation of IF signals for bidirectional RF testNI.

  • FPGA Reconfigurability: User-programmable FPGA enables real-time custom signal processing (filtering, modulation, demodulation)NI.

  • Integrated DDC/DUC: Digital downconverters (input) and upconverters (output) with 20 MHz bandwidth reduce host CPU loadNI.

  • High Dynamic Range: 14-bit ADC/DAC and low noise floor ensure accurate capture of weak RF signals.

  • Real-Time Streaming: Peer-to-peer data transfer enables low-latency SDR and spectrum monitoring applicationsNI.

Application Scenarios

  • Software-Defined Radio (SDR): Prototyping and validation of custom communication waveforms (5G, LTE, RFID)NI.

  • Spectrum Monitoring & Analysis: Real-time wideband spectrum surveillance, signal detection, and interference analysisNI.

  • RF Component Test: IF-level characterization of mixers, amplifiers, filters, and frequency converters.

  • Aerospace & Defense: Radar signal processing, electronic warfare (EW) simulation, and SIGINT systems.

  • Wireless R&D: Rapid prototyping of MIMO transceivers, beamforming, and adaptive communication systemsNI.

Usage and Maintenance Instructions

Installation and Configuration

Insert the module into an empty 3U PXIe chassis slot and secure the front-panel latch. Connect IF In/Out to the DUT using SMB cables, and Ref In to a 10 MHz external clock (optional). Power on the chassis; NI-MAX will auto-detect the module. Configure sampling rate, bandwidth, and trigger settings via NI-5640R driver before operationNI.

Operation Guidelines

Allow a 10-minute warm-up before precision measurements. Do not apply input signals exceeding +5 dBm to avoid ADC damage. Use LabVIEW FPGA to develop custom processing IP, ensuring FPGA bitstreams are validated for timing closure. For multi-module synchronization, enable NI-TClk and align trigger edgesNI.

Daily Maintenance

Keep SMB connectors clean and dry; tighten cables gently to avoid pin damage. Inspect cables and connectors monthly for wear or corrosion. Perform annual external calibration to maintain accuracy. When not in use, power off the module, disconnect all cables, and store in an ESD-safe environment. Avoid exposing the module to extreme temperatures or humidity.


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